Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

ALTLVDS_RX Old & New

Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I did not think that was the case. Again, the hard IP is the same. I opened both versions, launched altlvds_rx megawizard/qsys for Cyclone V, made the deser /8, clicked on external PLL and they both say the same thing. Can you copy the two messages your looking at here and also put where they're coming from?

I think there are multiple ways to do it as long as the relationship stays the same. I'm almost postiive the frequencies must be the same between versions(one fast, one parallel, and one parallel with small duty cycle for enable)