Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorThanks for the response.
I'm using Cyclone V with true LVDS, 8 bit deserialization, 320Mbits/s data rate. In my post I just reported what the MegaWizard GUI was telling me. A single clock is required for Quartus 13.1, and two clock are required for Quartus 16.1. I'm guessing Altera simply redesigned this IP and changed the way it operates.
