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Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorWhat device are you using(and if it has True LVDS, are you using it), and what's the deserialization factor(deser of 2 does not use true LVDS but DDIO structure, and runs much slower). What speed?
Never fully trusting myself, I generate an altlvds with internal PLL, then go to the Fitter Report's PLL Usage and see what the clocks are doing, and make my external PLL do the same. If you post that here we might be able to shed some light.
