altlvds pll clock timing constraints

Thanks again,

perhaps this needs to be addressed to Altera support. My problem is that the clocks are generated by Altera IP (within the altlvds megafunction) and/so there is little I can or know how to do to get to the bottom of any internal timing problems. I think I'll make a support request and see what they have to say. I am confident that I'm not pushing the device beyond it's performance limits (which could have been a possibility).

Dave W.