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Honored Contributor
Honored Contributoraltlvds pll clock timing constraints
Hello, I'm getting a hold slack violation between clock outputs on the PLL used by an altlvds_rx module. clk0 output is 300MHz and clk2 is div 7 or 42.86. My question is, should I be includi...
Altera_ForumHonored Contributor
Honored ContributorI believe the derive_pll_clocks adds a multicycle on the paths from the SERDES into the fabric. This should be accurate and help your timing.
