altlvds pll clock timing constraints

Thankyou,

actually, I think there is something in what you have suggested. I seem to remember running derive_pll_clocks in TimeQuest and getting a list of multicycle type messages as well as the list of pll clocks. To be honest, I don't understand them very well but I'll try it again and post the results.

It's a SERDES so there is a transfer of a word on every 7th clock cycle. That's why I was unsure whether or not the clocks should be in the same group.