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Altera_Forum
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9 years ago

ALTLVDS does not seem to use DDIO/DDR with its PLL clock?

Hello, I am trying to create and compile an ALTLVDS megafunction for 4 lanes, of deserialisation factor 7, frequency 74.25, as such data rate 519.75. I have the Cyclone V: 5CGXFC4C7U19C8 device...
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Altera_Forum
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9 years ago

Hello,

Thanks for the quick response and sorry for me replying so late. I have tried to recreate the configuration you wrote and I failed, till by trial and error I realised that the problem was that I set an illegal phase shift value. It did not pop up in the error messages, so I guessed it wasn't the problem.

Now that I carefully read this solution https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09202013_385.html , the megafunction compiles.

Thank you for your help.