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Altera_Forum
Honored Contributor
Honored ContributorALTLVDS does not seem to use DDIO/DDR with its PLL clock?
Hello, I am trying to create and compile an ALTLVDS megafunction for 4 lanes, of deserialisation factor 7, frequency 74.25, as such data rate 519.75. I have the Cyclone V: 5CGXFC4C7U19C8 device...
Altera_ForumHonored Contributor
Honored ContributorI quickly threw this project together in Q16.1 with a 600Mbps altlvds receiver in CV -8. No errors.
