ALTLVDS does not seem to use DDIO/DDR with its PLL clock?

For devices before Cyclone V, there was no true SERDES and it had to use DDIO registers. The problem is that this solution gets slower and slower at smaller geometries(due to larger On-Die Variation). Because of that Cyclone V has the dedicated SERDES and dedicated altlvds clock tree. For this implementation, it uses a dedicated clock tree for the fast clock that only drives the SERDES. To get better performance it uses a single register to capture the data, and the clock runs at the full data rate(this avoids rise/fall variation, thereby improving performance).

The Cyclone V -8 altlvds receiver is spec'd to run at 640Mbps, and so the clock from the PLL that drives the altlvds clock tree runs this fast. (The PLL output frequency max is probably a factor of how fast a global clock tree can run, not this altlvds). So what you're doing sounds right and I am fairly certain should work.

(If you go to a serialization of /2, it will use the DDIO and a global clock tree, so the clock rate will be cut in half, but once you start entering timing constraints it will fail timing, so I would avoid that)