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Altera_Forum
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13 years ago

altera tse mac signal ff_tx_rdy

Hi I am using tse mac ip for ethernet and i am getting rx side of sop & eop properly but i am getting the ff_tx_rdy low. when rx side of sop is always low & eop is properly getting in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've never really paied attention to those, just using what Altera put in their driver

      IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse.mi.base, 8);
      IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse.mi.base, 8);
      IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse.mi.base, 8);
      IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse.mi.base,  3);
      IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse.mi.base, tse_hw->tse_tx_depth - 16); //1024/4;  
      IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse.mi.base,  0); //32/4; // start transmit when there are 48 bytes
      IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse.mi.base, tse_hw->tse_rx_depth - 16); //4000/4);
      IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse.mi.base,  0);

It seems that you are using the correct value. I don't really understand how they influence the core's functionality, but the multiple comments on tx_section_full seems to show that Altera isn't sure either ;)

It may be a stupid question but are you sure that the tx path is enabled? You can check it by reading Command_config Register. Do you reset the TSE after changing the fifo registers? Altera recommends a reset after a speed change, but it could be useful too when changing the fifo registers.