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The tx_clk and rx_clk can be connected to any type of clock, just ensure that the tx and rx signals you are connecting to the TSE are synchronized with those clocks.
Is the MAC receiving also the correct clocks on the PHY side?
How is your ff_rx_rdy signal when you connect the tx signals to FPGA pins?
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Thanks Daixiwen.
The ff_rx_rdy signal is good - high - throughout and the ff_rx_data keeps receiving the data properly from the ethernet side. It is only the TX.
Now, I did one experiment. I took the working - loop backed tx and rx - project and change the tx_almost_full value to 3. The ff_tx_rdy again became permanently low.
I realise I do not understand the fifo thresholds properly. I intend to and am using the MAC in CUT THROUGH mode.
I have set up the fifo depth to 2K. I am using a 484 pin Cyclone iV 75 GX part.
What is the recommended values I should use to program the fifo thresholds? There seem to be four variable - the almost full, section_full, almost_empty and section_empty. For cut through mode I have set the section_full to the value 16 ( although I dont understand why, I have just done what the data sheet says).
Only when the other three seem to be at the hardware reset value (0) the loop back project seems to work. If I change these values it does not work. Once we set the cut through mode what is the relevance of the other variables?
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