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Altera_Forum
Honored Contributor
Honored Contributoraltera tse mac signal ff_tx_rdy
Hi I am using tse mac ip for ethernet and i am getting rx side of sop & eop properly but i am getting the ff_tx_rdy low. when rx side of sop is always low & eop is properly getting in ...
Altera_ForumHonored Contributor
Honored ContributorThe tx_clk and rx_clk can be connected to any type of clock, just ensure that the tx and rx signals you are connecting to the TSE are synchronized with those clocks.
Is the MAC receiving also the correct clocks on the PHY side? How is your ff_rx_rdy signal when you connect the tx signals to FPGA pins?
