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It looks like the transmit FIFO gets full and can't accept more data, that's why the ready signal becomes low. Now I don't know why the FIFO gets full and doesn't empty itself. Could you have a look at the signals between the MAC and the PHY? Is it trying to send anything? What kind of Ethernet link are you using? Is it full duplex?
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Thanks. the full flag is indeed high. We are using full duplex. PHY is Marvel 88E1111 gigabit. TSE MAc is instantiated in SGMII triple speed mode.
This problem goes away when I loop the MAC ff_rx signals to the ff_tx signals and keep the ff_rx_rdy to high.
It also goes away when I connect the tx signals to a packet generator within the same FPGA.
When I open up the tx data signals, and take them to the FPGA pins, the tx ready goes low and fifo full flag goes high.
Question: At reset, is there any recommended levels at which the tx input lines including the clk to be held at? Should I control the tx_clk and rx_clk in any way? currently it is connected to a free running 50 MHz.
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