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Altera_Forum
Honored Contributor
13 years agoaltera tse mac signal ff_tx_rdy
Hi I am using tse mac ip for ethernet and i am getting rx side of sop & eop properly but i am getting the ff_tx_rdy low. when rx side of sop is always low & eop is properly getting in ...
Altera_Forum
Honored Contributor
13 years agoIt looks like the transmit FIFO gets full and can't accept more data, that's why the ready signal becomes low. Now I don't know why the FIFO gets full and doesn't empty itself. Could you have a look at the signals between the MAC and the PHY? Is it trying to send anything? What kind of Ethernet link are you using? Is it full duplex?