altera_reset_synchronizer_int_chain_out

Fitting DSP blocks should be a trivial exercise, i.e. if they're are 700 blocks in the device, it should fail if you have 701 in your design, and fit with 700. (I'm talking about actually placing them. You might have routing issues or something else later on). What I have seen change in designs is the global promotion, where sometimes a signal like a clock gets promoted to a regional clock tree, but the clock feeds more DSP blocks then available in a quarter of the device. (I just saw one with a peripheral clock tree.) In these cases the error message looks like yours, but then gives the names of all the DSP blocks and says the region they couldn't fit into. Note that it will be something like, "CUSTOM_REGION_X44_Y0_X88_Y36" or something like that, which isn't a global clock tree name, but the area it covers, i.e. from X44 to X88 and from Y0 to Y36(I'm just making up the number ranges, but if you look in the chip planner it corresponds to a clock tree). If this is the case, go to the Global Signals section of the fitter report and see what was assigned to a clock in this region and drives the stated DSP blocks and then assign it to a larger clock tree in the Assignment Editor.