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Thank you. So if i want to use Altera ethernet ip core i have also to use Avalon bus core? And my business-logic core has to interact with Avalon bus core (so i need some adapter core)?
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It depends on your implementation, it may or may not be needed. I believe you can use Nios to read back from the memory location that your IP is working on - but with Avalon adapter wrapped around you logic, you have the ability to handle back pressure and manage interrupts. This is just my thoughts - perhaps there are better explanation out there.
Meanwhile, if you are using SoC and are running Linux on the ARM core, you can read/write to your FPGA IP via one of the HPS-to-FPGA bridges that uses AXI interface.
Hope this helps...
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