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Honored Contributor
Honored ContributorAltera DE2: LVDS bit alignment issue
I'm trying to verify whether my FPGA board (Altera DE2) can support LVDS. For this purpose, I set up a simple system to test it, using an ALTLVDS_TX module to output to a GPIO pair, which is then con...
Altera_ForumHonored Contributor
Honored ContributorYou will need something against which you can frame the data. So, yes - perhaps a frame clock might work. However, I think you've already found that you hadn't predicted the alignment of the rx data. So sending a framing clock that is generated separately to the tx/rx IP will prove impossible to align to. The fact that the ALTLVDS_RX offers a bit slip option tells us that the alignment is not predictable. There's no telling at what point in the received stream the ALTLVDS_RX will even lock. So the alignment is unpredictable - hence the need for the bit slip circuitry.
I think you'll end up needing to add framing to the 8-bits of data you're carrying. You may only need to add one bit that's static and search for that. Cheers, Alex
