Altera DE2: LVDS bit alignment issue

You will need something against which you can frame the data. So, yes - perhaps a frame clock might work. However, I think you've already found that you hadn't predicted the alignment of the rx data. So sending a framing clock that is generated separately to the tx/rx IP will prove impossible to align to. The fact that the ALTLVDS_RX offers a bit slip option tells us that the alignment is not predictable. There's no telling at what point in the received stream the ALTLVDS_RX will even lock. So the alignment is unpredictable - hence the need for the bit slip circuitry.