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Honored Contributor
Honored ContributorAltera DE2: LVDS bit alignment issue
I'm trying to verify whether my FPGA board (Altera DE2) can support LVDS. For this purpose, I set up a simple system to test it, using an ALTLVDS_TX module to output to a GPIO pair, which is then con...
Altera_ForumHonored Contributor
Honored ContributorYour receiver doesn't know how to align itself to your incoming data. You need to control the receiver and tell it where to align itself to.
Have a look at the 'rx_data_align' port option in the ALTLVDS_RX Parameter Settings. See 'Table 10. ALTLVDS_RX Input and Output Ports' of the "lvds serdes transmitter/receiver ip cores user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altlvds.pdf)". If you're only sending the 8-bit counter value then you've nothing to look for to align to. You will need to frame your data with something your receiver logic can look for and then control the receiver's bit slip until you are aligned as required. Cheers, Alex
