Altera CPLD Max V (P/N: 5M2210ZF256C4)

Question

I am supplying this CPLD from two separate power rails (A 1.8V rail and a 3.3V rail). The CPLD uses 1.8V for VCCI02 through VCCI04, and uses the 3.3V rail for VCCI01. The 1.8V rail starts up in about 1ms, and the 3.3V rail starts up in about 20-40ms. Will the component have issues since the two supplies are not coming up to voltage simultaneously?

amint_intel · Answer

Hello,I see that you have already posted similar forum thread: https://community.intel.com/t5/Programmable-Devices/Altera-CPLD-Max-V-P-N-5M40ZE64C4/m-p/1386724#M85027I think you can continue there since the answer will be similar.Thank you

Forum Discussion

Altera CPLD Max V (P/N: 5M2210ZF256C4)

1 Reply

Recent Discussions

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices

Avalon-ST configuration with Agilex 3 fails

Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required

MAX10 DDR3 Timing