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Recently I discovered in the datasheet of ALTDDIO_OUT that the output cannot be reused in the FPGA and it is only for outputting. Is this the reason SignalTap which is implemented on the FPGA as part of the FPGA configuration cannot look at this signal?
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The output clock is inside the IO element so I am not surprised you were unable to monitor it with SignalTap. I would recommend using the Chip Planner and Resource Property Editor in Quartus to learn about the architecture looks and how your design is implemented.
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Why not? Is not SignalTap telling me in relation to the sample-time at which point of time (sample) signals will be driven? The only problem I see is because of too low sample rates that the signal will be HIGH before the next edge tells me it is gone HIGH.
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There are several reasons. If you want a perfect picture of the timing you need to connect an oscilloscope on the physical pins, as opposed to SignalTap which works inside the FPGA fabric. For example, you will miss delays introduced by the delay elements in the IO elements, package bonding, etc. Assuming you are sampling with an unrelated clock, the delay from the monitored signals to the SignalTap core will differ from signal to signal and distort the picture. There are probably several other reasons why this is a bad idea.
Another point is that process, temperature and voltage variations play a big role in the delays you observe. (If you study the waveforms in TimeQuest reports you will see that a lot of the margin is lost to uncertainties.) Hence, even if you compile a design and measure the timing to be perfect on one board with an oscilloscope, you could get very different results on a different board. The way to do this is therefore to make SDC constraints in accordance with AN433 rather than do measurements. If this is done right and timing analysis passes, the interface is guaranteed to work.
Note that it doesn't matter if you use the DDIO element for the clock or not as long as you define the correct timing constraints and timing passes. The idea with the DDIO element is to make meeting timing easier for the tool.
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