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if signaltap is sampling on 300MHz and you see input clk then yes it is not telling the truth about output clk.
BTW your instant name in signaltap is different from name in design. Could it be your are looking at wrong instance that does not drive output.
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Dear Kaz,
no, sorry for this confusion, this is no mistake. I posted the original code from Cypress. In my project the instance name is the one you can see in SignalTap. BTW when outputting clk_out out of the chip into an LED on the Cyclone V GX Starter Board the LED is blinking when I choose relativly low clockrates. Recently I discovered in the datasheet of ALTDDIO_OUT that the output cannot be reused in the FPGA and it is only for outputting. Is this the reason SignalTap which is implemented on the FPGA as part of the FPGA configuration cannot look at this signal? I wonder if anybody else here experienced sometimes this problem in the past.
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No you can't measure delays at io using signaltap.
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Why not? Is not SignalTap telling me in relation to the sample-time at which point of time (sample) signals will be driven? The only problem I see is because of too low sample rates that the signal will be HIGH before the next edge tells me it is gone HIGH.
Kind regards and thank you so far.
Honored Contributor
