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DDIO clock output helps edge align dout with clkout as both data and clk are clocked by same clk 100MHz. For signaltap you need faster sampling to see clk 100 but you don't need to...
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Dear kaz,
I think that I'm already doing faster sampling (sampling clock is 300 MHz from pll) because I can clearly see the 100 MHz input clock into ALTDDIO_OUT. Please see attachment below.
https://alteraforum.com/forum/attachment.php?attachmentid=14523&stc=1 Do you think that SignalTap Scope is telling me the truth about dataout ? It always stays 0. :(
The reason for monitoring this signal is because I want to know if I hold the correct timing for all signals in relation to the 100 MHz for a slave fifo interface (cypress fx3) like required by the FX3 datasheet for slave fifo implementation, see second attachment below.
https://alteraforum.com/forum/attachment.php?attachmentid=14524&stc=1 Kind regards
Honored Contributor
