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Dear all,
i have an example FPGA configuration project for a FIFO interface. It is for a Cyclone 5 device and is comprised of a fifo interface, an ALTDDIO_OUT and a pll. The FPGA should act as master interface and for this reason a 100 MHz clock is outputed of the chip to an USB 3.0 slave interface with the clock input and a 32 bit INOUT.
What is the reason that the 100 MHz clock coming out of the chip is routed through the ALTDDIO_OUT ? I know there is an instruction from altera AN433 which basically states there are different ways to output the CLOCK off the chip, but I cannot see a specific reason for choosing the ALTDDIO_OUT?
The ALTDDIO_OUT is instantiated this way:
ddr_inst_to_send_out_clk_to_fx3 : ddr
port map(
datain_h => '0',
datain_l => '1',
outclock => clk_100,
dataout => clk_out
);
Is there a way to tap into the clk_out signal with SignalTap II ? It always stays '0', but I can see the clk_100 input clock to the ALTDDIO_OUT. Or is there a problem in SignalTap 2 when working with a high frequency sample clock. In the past I recognized that when I choose for the source clock a frequency of 200 MHz some displayed signals are jittering/changing from 0 to 1 very fast even when they should stay on '1' for some time.
Thank you for your help.
Kind regards
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DDIO clock output helps edge align dout with clkout as both data and clk are clocked by same clk 100MHz. For signaltap you need faster sampling to see clk 100 but you don't need to...
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