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Altera_Forum
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10 years ago

ALTDDIO - 16bitx250MHz to 32bitx125MHz - Proper Timequest timing closure?

Hi, I'm using ALTDDIO to convert source-synchronous 16-bit/250 MHz data to 32-bit/125 MHz data. The device is a Cyclone V E. I'm trying to figure out how to properly constrain this interface. I have ...
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Altera_Forum
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10 years ago

Correct me if wrong but if your data @250MHz is SDR, I don't get it how and why you change it to DDR inside FPGA using DDRIO