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Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored ContributorFirst post was because I was registering the LVDS output outside in the FIFO.
Now I am trying to register the outputs using the LVDS Megafunction as suggested in earlier posts. And the LVDS IP set the multicycle constraints itself. Not me. I only set up input clock with 90 phase and input delay constraints. Which shouldn't affect core-clock timings. Something tells me its just because there are 8 LVDS Rx channels. It can meet timing on some of the registers. But not on all of them..
