ALT_LVDS timing fails for core clock

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I do have an sdc. Define the clock inputs. Set the input delay based on setup and hold times.

And have derive pll clocks in it too.

I'll paste it tomorrow morning from the lab.. But its a simple constraints. Took it from the DDR cookbook from the wiki.

I was wondering if giving LVDS megafunction the fast bitclk as clock input would be better or giving it the slow frameclock is better.. And if that makes it quirky..

Hope this helps.

ZubairLK

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if you have option of registered output on rx lvds then that must be checked. It could be they are not registered and data path is from from bitclk to fifo