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Honored Contributor

12 years ago

ALT_LVDS timing fails for core clock

Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...

multiple-attachments.zip1.3 MB

Altera_Forum

Honored Contributor

12 years ago

I believe there is a multicycle from the slow to the fast domain. Try adding "derive_pll_clocks" to your .sdc, as I think that will add it.

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ALT_LVDS timing fails for core clock

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