ALT_LVDS timing fails for core clock

I am only receiving data from the LVDS_Rx megafunction

ADC sending 12 bit serialized data at 480Mbps.

Clock at 480Mhz as well.

I intend to use 6 bit SERDES. And will mux the data later to form 12 bits.

8 channels of serialized data goes into the LVDS_Rx megafunction.

6 bit deserializer

480Mhz clk input

the clk_output from the LVDS_Rx megafunction is 80MHz and goes into the write clock of a DC FIFO.

The deserialized data output from the LVDS Megafunction goes into the data input of the DC FIFO.

Timing fails at this point.

The data output from the LVDS_Rx megafunction. I don't know why.

For some reason, timequest says the LVDS_Rx megafunction deserialized data 'output' is clocked at the fast clock (480MHz). and is being latched at the slow clock (80MHz) on the DC FIFO side.

Hope this explains

ZubairLK