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Altera_Forum
Honored Contributor
Honored ContributorAll stx 2 running on single clk pin(no ppm offset)
Hi Im new to altera FPGAs. I went throughout Stx II handbook but one thing is still not clear to me whether is possible. Can I run the entire device based on one fast PLL whic...
Altera_ForumHonored Contributor
Honored ContributorI do NOT think you can (should) do this.
Check the jitter spec's omn the PLL's you are looking to use. The cascaded PLL's may not ALWAYS lock in all cases I believe. Instead, use an external clock multi output driver ship and feed the PLL's from their appropriate input pins.
