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Altera_Forum's avatar
Altera_Forum
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14 years ago

"alias" problem in fixed_pkg

sir, i am using fixed_pkg_c.vhd.during synthesis it gives error on alias statement.if i remove this "alias " only, it gives error

".

ERROR:HDLParsers:164 - Line 1024. parse error, unexpected IDENTIFIER"

the program copy where it gives the error is "function to_slv (

arg : UNRESOLVED_ufixed) -- fixed point vector

return STD_LOGIC_VECTOR;

to_StdLogicVector is to_slv [UNRESOLVED_ufixed

return STD_LOGIC_VECTOR];

to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed

return STD_LOGIC_VECTOR];

-- plz sir help me.............:cry:

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    then sir how will i rectify error occured due to "alais" statement?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    then sir how will i rectify error occured due to "alais" statement?

    --- Quote End ---

    You never said what the error with the alias statement was - just that you deleted the word "alias".

    Secondly - your project is a Xilinx project. We cannot help you with that - this is an altera forum.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    sorry sir,now i don't remove alias. now how will i rectify the error?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You still havent said what the error is.

    Looking at your code you have this line:

    n1 <= to_ufixed(.46,n1);

    change it to

    n1 <= to_ufixed(0.46,n1);
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    After correcting the syntax error mentioned by Tricky, the code compiles in Altera Quartus. The synthesized gate level logic looks somewhat trivial, but is correct, because 0.46 rounds up to 0.5 which isn't but a bitshift.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    @ triky sir,

    my code is :

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.NUMERIC_STD.all;

    use WORK.math_utility_pkg.all;

    use work.fixed_pkg.all;

    entity nitu is

    Port ( a : in ufixed (2 downto 0);

    c :out ufixed (2 downto -3));

    end nitu;

    architecture Behavioral of nitu is

    signal n1 : ufixed (0 downto -3);

    begin

    n1 <= to_ufixed(.46,n1);<---------- ERROR LINE.:oops:

    c <= a *n1;

    end Behavioral;

    ERROR :Line 42. parse error, unexpected POINT.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    @triky sir , after correcting as per your advice (i.e 0.46 instead of .46),it gives error that :line 1031: alias of a function is not supported.

    at the line :

    function to_slv (

    arg : UNRESOLVED_ufixed) -- fixed point vector

    return STD_LOGIC_VECTOR;

    error -------> alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed

    return STD_LOGIC_VECTOR];

    alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed

    return STD_LOGIC_VECTOR];
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As said, the code compiles in Quartus, so it's apparently a Xilinx XST related problem. Ask the Xilinx guys.