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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Agilex F-Tile tx_ready fails to assert

I'm starting a new thread, because the previous discussion was booted into the void: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Agilex-Ftile-is-not-asserting-tx-ready-after-the-reset-seq...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


To debug your design, you have to share your design. Don't worry about the Quartus version. Please just mention the version you build the design. So, that I will debug your design in that same version.


Thank you,

Kshitij Goel