Forum Discussion
jmcguire3
Occasional Contributor
Occasional ContributorAgilex F-Tile tx_ready fails to assert
I'm starting a new thread, because the previous discussion was booted into the void: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Agilex-Ftile-is-not-asserting-tx-ready-after-the-reset-seq...
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
To debug your design, you have to share your design. Don't worry about the Quartus version. Please just mention the version you build the design. So, that I will debug your design in that same version.
Thank you,
Kshitij Goel
jmcguire3Okay, took a while to figure out what I think you want ... a .qar archive with the "service request" features enabled, right?
Archive and log files are attached.
