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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Agilex F-Tile tx_ready fails to assert

I'm starting a new thread, because the previous discussion was booted into the void: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Agilex-Ftile-is-not-asserting-tx-ready-after-the-reset-seq...
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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Correction: went back and double-checked. Tx_Ready *did* assert with the SystemPLL set to 78.125MHz. Haven't seen that happen in this configuration until now.

But the outputs are still all-zeroes. Something else is still suspending proper operation.