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Honored Contributor
Honored ContributorADC, DAC problem in audio codec
Hy, I want to configure in ADC and DAC mode the audio codec. I want fs=48khz, so i need a fmclk=12.288mhz. How can i obtain sa 12.288 mhz frequency from 50 mhz clock? Is it ok is i di...
Altera_ForumHonored Contributor
Honored Contributoryou still won't get 12.288 MHz with a PLL. a quick test on a CII shows the closest achievable clock is 12.345679 MHz. i think all this means is that you won't actually get to 48 ksps, in this case it looks like 12.345679 MHz / 256 = 48,225.3086 ksps (depending on the mode).
