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Honored Contributor

9 years ago

accelerate cyclone V

Hi All, I am using cyclone V SOC kit from Terasic. Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to funcation with low latency. I mad...

Altera_Forum

Honored Contributor

9 years ago

The highest speed interface is FPGA-to-SDRAM because you get multiple ports and in the case of Cyclone V SoC you can gang them together to make a wider interface.

You might find this design to be useful if you don't have plans on having a Nios over on the FPGA side of the device, unfortunately it only targets Arria 10 SoC though: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

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accelerate cyclone V

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