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Honored Contributor
Honored ContributorAbout the FPGA
I need to make my FPGA automatically to read the .hex fire (which is a test program) when I synthesis my CPU core (openMSP430) to the FPGA. Where should I put this hex fire ,in the FLASH or SDRAM, an...
Altera_ForumHonored Contributor
Honored ContributorIf I still want to use SDRAM or FLASH as memory, can some tell me how to change the OpenMSP430 code to connet the memory and CPU core? create another fire as top fire which contain the control signal of the memory (SDRAM and FALSH) and also the openMSP430 top level?
