Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAbout PLL output to driver DAC from top to bottom
A DAC chip on board needs clock but this DAC located near FPGA bottom. Now I conter the problem: how to design a clock network that driver the DAC from the PLL output pin of the chip, while the ...
Altera_ForumHonored Contributor
Honored ContributorI guess, the data outputs are also near the DAC? Generally, it can't be avoided in many designs to route clocks and other fast signals "crisscross" the logic array. This may cause additional effort for place&route tools, but is succesful in most cases. At worst, you can precompensate a systematical routing delay through PLL phase shift.
