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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

About pin states from the end of MAX10 configuration to transition to user mode

According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach ...
Configuration
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


After configuration complete, if you define the initial state of the design '0', A B C or D will be '0'. If you define it as '1' then the state is '1'. But for your information, before that happened, all of this are in tri state, hence it cannot be modified.


Regards,

Aiman