Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout pin states from the end of MAX10 configuration to transition to user mode
According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach ...
NurAiman_M_Intel
Super Contributor
Super ContributorHi,
After configuration complete, if you define the initial state of the design '0', A B C or D will be '0'. If you define it as '1' then the state is '1'. But for your information, before that happened, all of this are in tri state, hence it cannot be modified.
Regards,
Aiman
