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Altera_Forum
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15 years ago

A timing closure problem.

I have suffered a timing closure problem. I use the Arria II GX device and Quartus 10.1 without SP . In my design , I use the DSPBuilder ADV Block create a IP. In the IP , after the inputs pass throu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The figure give the data arrival path with the worst slack. Based on your suggestion , I explored my design and found the fan in to the combinational block is not too much. But after using the command your suggested to analyze the failing path. I found that there are too much intermediate nodes for the failing path. These nodes need a lot of lcell to fit , and will make the path between source and destination go through several LAB , and not a LAB. Thanks , Rysc.