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Honored Contributor
Honored ContributorA timing closure problem.
I have suffered a timing closure problem. I use the Arria II GX device and Quartus 10.1 without SP . In my design , I use the DSPBuilder ADV Block create a IP. In the IP , after the inputs pass throu...
Altera_ForumHonored Contributor
Honored ContributorI have fixed this problem by inserting one level register before the IP's input register and applying retiming for them. But I just need some help for me to master how to use the options and the logiclock technich of Quartus to improve the IC type timing performance. Thanks.
