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Altera_Forum
Honored Contributor
Honored ContributorA problem with DDR2 and PLL core in SOPC
In my SOPC design(Quartus II 10.1), both Avalon_altpll and DDR2 controller are used. And I can generate the nios core successfully. However, when I compile the whole design, the software always warni...
Altera_ForumHonored Contributor
Honored ContributorThat was quick... I found that it was some previous (corrupt?) instance of a pll that did not allow to implement a pll after that. I deleted all the previous pll files, and now it works
