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Altera_Forum
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15 years ago

4-QAM output error

Hi, I am trying to build a 4-QAM on an Altera FPGA and am having problems with the simulation on ModelSim. Attached to this thread is my code "qam4.vhd" which is the 4-QAM code and "testb...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks Kaz for the reply and help, but somehow, I am still getting errors in the results =( as attached in the file " QAM4_ModelSim_error_21_04_2011.jpg"

I noticed that my output takes up 2 clock cycles each, which I don't understand why this is happening.

Will you help me to look through the file? I am pretty new to VHDL and I really want to solve this problem. Attach is the file amended as you recommended. Thanks again, really appreciate your help.