10663 parameter or port？

Hi,

here, you have used the 'DIVPA' parameter for instantiation of module 'clkdiv' & it might not be legal.

please refer the 'Verilog LRM' for '3.4 Parameters ', here it is mentioned that It is not legal to use hierarchical name referencing (from within the analog block) to access external analog variables or parameters.

https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf

Regards,

Vicky

Hi,

May I know any update or Should I consider that case to be closed?

Regards,

Vicky