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Honored Contributor
Honored Contributor10170 Verilog Error
module tcounter (CLK, CLR, ENP, ENT, Q); input CLK; input CLR; input ENP; input ENT; output [3:0] Q; wire [3:0] inc; treg4bit register( .CLK(CLK), .IN(inc), .RES...
Altera_ForumHonored Contributor
Honored ContributorI say this in the nicest possible way - you need to find a good book or tutorial on how to write Verilog code. this (http://www.asic-world.com/verilog/verilog_one_day.html) is a good starting point.
