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Honored Contributor
Honored Contributor10170 Verilog Error
module tcounter (CLK, CLR, ENP, ENT, Q); input CLK; input CLR; input ENP; input ENT; output [3:0] Q; wire [3:0] inc; treg4bit register( .CLK(CLK), .IN(inc), .RES...
Altera_ForumHonored Contributor
Honored ContributorHi mage76,
there are several issues in your example: As inc is a wire, you need an assign statement for logic. Or define inc as reg, then you could use always @*. 'inc' (as reg) is not initialized, this will infer latches, i am sure you don't want this! Or use inc as reg in combination with 'always @(posedge CLK)', this will infer FFs instead of pure combinatorial logic. If your intention is to create combinatorial logic only you should use '=' instead of '<='.
