Forum Discussion
Contributorwill 64bit EMIF works with a 72 bits DDR4
Hi David,
In case you're doing some demos, I think it's good for you to create an EMIF example design with Arria 10 Dev Kit preset where you can choose the preset in the EMIF Parameter Editor.
The preset will set the parameter that match to the Arria 10 Dev Kit.
The 72 bits = 64 bits Data + 8 bits ECC.
If you enabled the ECC in your configuration, then you will have 72 bits interface.
Else your interface should be 64 bits.
-Adzim
Regular ContributorHi David,
In case you're doing some demos, I think it's good for you to create an EMIF example design with Arria 10 Dev Kit preset where you can choose the preset in the EMIF Parameter Editor.
The preset will set the parameter that match to the Arria 10 Dev Kit.
The 72 bits = 64 bits Data + 8 bits ECC.
If you enabled the ECC in your configuration, then you will have 72 bits interface.
Else your interface should be 64 bits.
-Adzim
dsun01Hi AdzimZM
Thank you for your explanation, I have questions while I implement this 72bits EMIF qsys. If I use the presets emif_0 from Arria 10 GX FPGA Development Kit with DDR4 HILO form FPGA(72). as in the picture, the EMIF to Avalon bus will be 576 bits. but the data from the ADC is 512 bits. where and how to convert this 512 bits data to 576 bits.
Thanks
David
- dsun01
if we enable the ECC feature, then the data path to the upstream will be set to 64 instead of 72. thank you.
