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Ozzuu's avatar
Ozzuu
Icon for New Contributor rankNew Contributor
6 years ago

Which peripherals are using top 64 MB of HPS DDR?

I am using cyclone V with 1GB DDR. When I try to run a baremetal application from OCRAM to read and write to every possible address of DDR, it always fails on top 64 MB. I tried searching in the HPS ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

This is the address map from the processor's point of view, so yes, the top 64 MB is used by the items listed.

#iwork4intel

  • Ozzuu's avatar
    Ozzuu
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks for your reply but I don't think that is correct. I think the statement in the manual is referring to FPGA DDR address space, starting at 0xC0000000.

    FPGA slave region is anyway of size 960 MB (1024 MB - 64MB), which confirms that the top 64 MB of FPGA DDR is being used by the things mentioned above.

    Also, there is a typo in that statement, 1024MB - 64 MB = 960 MB, (which in hex is 0x3C000000 and not 0x3FFF0000).

    I also made a mistake while posting, my application fails for top 64 KB (starting from 0x3FFF0000). So now the question is, are there any peripherals using top 64 KB of HPS DDR?

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      Hi,

      The top 64MB of address space is the HPS peripherals region.

      The HPS peripherals region is always allocated to the HPS dedicated peripherals for the Cortex-A9 MPU subsystem.

      Regarding the 64 KB on the boot region:

      The boot region is 1 MB in size, based at address 0. After power-on, the boot region is occupied by the boot ROM, allowing the Cortex-A9 MPCore to boot.

      Though the boot region size is 1 MB, accessing beyond 64 KB are illegal because the boot ROM is only 64 KB.