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I'd like to revive this page. Someone might have new answers about this. I've just realized that the SDRAM in DE2-115 is not a DDR one so none in the MegaWizard IP works.
In this tutorial, the SDRAM was used along side NIOS. I don't want to use NIOS like the thread starter.
ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/vhdl/de2-115/using_the_sdram.pdf Any insights on how to implement the SDRAM without NIOS?
In Chapter 9: Implementing and Parameterizing Memory IP 9–3 Design Flow of this handbook (
http://www.altera.com/literature/hb/external-memory/emi_plan.pdf), it showed two possible ways to generate the IP. One using the Qsys and the other using the MegaWizard. Can someone share their knowledge on how to create a complete IP of the SDRAM Controller using Qsys with AVALON interface as the controlling component?
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I am trying to do the same for distributed processing. The ISSI chip on the DE2-115 is Single Data Rate (SDR) SDRAM. There is an SDRAM Controller available from the IP Catalog under the following in Qsys:
Memory Interfaces with ALTMEMPHY>SDRAM>SDRAM Controller.
You would then export the signals to the external RAM chip and connect the in/outputs in your toplevel VHDL or Verilog file. To interface with the chip, you would have to adhere to the Avalon-Memory Mapped interface specification, which is standard and would be the same way you would interact with on-chip memory (See the Avalon Interface Specificaitons document or look for some examples).
One thing that you must remember is that the SDRAM chip clock DRAM_CLK leads the system clock CLK_50 by 3 nanoseconds on the DE2-115. You may have to include a Phase Lock Loop (PLL) module to adjust for the offset. This is described when interfacing with the Nios II and should hold for custom logic as well due to off-chip latency. Hope that works!
The document "Using the SDRAM on Altera’sDE2-115 Board" has that timing detail as well as an example with the Nios II as reference.
(please rep if you find helpful =)
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