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DP7's avatar
DP7
Icon for New Contributor rankNew Contributor
7 years ago

Using DDR3 memory without hard processor

Hi, I have Cyclone V E 5CEFA9F23C7. I need to sample ADC at very high speed (500MHZ) and stream it into an external DDR3 memory. I connected a clock and memory controller in the qsys. exported th...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

​ Hi DP7,

It is not necessarily to use the nios as the memory controller access using the AVMM interface. To generate the example design and run simulation, refer to this chapter 13.3 (Uni-PHY Based Example Design) of the external memory hadbook:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf#page=406

On the simulation, you can check the traffic pattern of the avalon mm interface.

Hope this helps.