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It was actually wonderful of you to throw some ideas. Throughout our brainstorming sessions, none of us found out about the upcoming JEDEC standard..
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Glad to hear that it helped.
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Thanks for the heads up. Embedding the frame clock within the signal could be tricky in that case.
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Yeah, I think it would be more trouble than its worth at this point.
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AD9671, an 8-channel ADC for Ultrasound applications is coming soon.
The preview page shows :
"the ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface."
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Alas, you often find a better part out there, or proposed ... usually after it is too late for the current project :)
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The DE3(Stratix III) does not have any transceivers. Would have simplified a lot of things if it did..
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Why not obtain a couple of DE4's then, or perhaps Stratix IV GX Development kits? The University Program might have an affordable option.
You'll need to tradeoff how much effort it'll take to get data from the DE3 to the Stratix V. You might find its easier to use the HSMC connectors on the Stratix IV kit to get ADC data into the FPGA, and then use the transceivers on the PCIe edge connector to get over to the Stratix V. Samtec have PCIe edge-connector to SMA breakout cables (I have some). I can give you the part numbers if you need them.
Cheers,
Dave
Honored Contributor
